POWERALU03, IYAD & ABHINAV

ILLINOIS INSTITUTE OF TECHNOLOGY

ECE 429 FINAL PROJECT

POWERALU03

Abhinav Gupta & Iyad Jafar

ABSTRACT

The main goal of this project titled “The Goldschmidt Division Power ALU” is to implement and design an 8-bit ALU which executes AND, OR, NOT, ADD, SUBTRACT, MULTIPLY and DIVIDE functions. All ALU functions execute on two’s complement fractional numbers. In this project, a systematic and organized approach is taken towards synthesizing the POWERALU03. All the blocks are designed in Verilog hardware descriptive language and then synthesized with the help of the standard cells and sophisticated tools such as Silicon Ensemble from Cadence Design Systems. All the details of the design process including the problems faced and chip fabrication have been documented and well explained.

   1.INTRODUCTION

   2.BACKGROUND

   3. DESCRIPTION OF BASIC UNITS

GENERAL PURPOSE REGISTERS

ACCUMULATOR

MULTIPLEXER

ADD-SUBTRACT UNIT

AND-OR-INVERT UNIT (AOI)

MULTIPLICATION

DIVISION ITERATION AND MULTIPLICATION

INITIAL APPROXIMATION UNIT

TWOS COMPLEMENT UNIT

ROUNDING UNIT

FINITE STATE MACHINE

ERROR UNIT

4.DESIGN FLOW

5.RESULTS & CONCLUSIONS

6. VERILOG CODE

7.REFERENCES

USEFUL LINKS

http:\\www.ece.iit.edu/~cad

http:\\www.ece.iit.edu/~jstine

IYAD JAFAR , [email protected]

ABHINAV GUPTA , [email protected]

COPYRIGHTS © 2003

	ILLINOIS INSTITUTE OF TECHNOLOGY
ECE 429 FINAL PROJECT POWERALU03 Abhinav Gupta & Iyad Jafar
ABSTRACT The main goal of this project titled “The Goldschmidt Division Power ALU” is to implement and design an 8-bit ALU which executes AND, OR, NOT, ADD, SUBTRACT, MULTIPLY and DIVIDE functions. All ALU functions execute on two’s complement fractional numbers. In this project, a systematic and organized approach is taken towards synthesizing the POWERALU03. All the blocks are designed in Verilog hardware descriptive language and then synthesized with the help of the standard cells and sophisticated tools such as Silicon Ensemble from Cadence Design Systems. All the details of the design process including the problems faced and chip fabrication have been documented and well explained.
1.INTRODUCTION 2.BACKGROUND 3. DESCRIPTION OF BASIC UNITS GENERAL PURPOSE REGISTERS ACCUMULATOR MULTIPLEXER ADD-SUBTRACT UNIT AND-OR-INVERT UNIT (AOI) MULTIPLICATION DIVISION ITERATION AND MULTIPLICATION INITIAL APPROXIMATION UNIT TWOS COMPLEMENT UNIT ROUNDING UNIT FINITE STATE MACHINE ERROR UNIT 4.DESIGN FLOW 5.RESULTS & CONCLUSIONS 6. VERILOG CODE 7.REFERENCES USEFUL LINKS http:\\www.ece.iit.edu/~cad http:\\www.ece.iit.edu/~jstine IYAD JAFAR , [email protected] ABHINAV GUPTA , [email protected] COPYRIGHTS © 2003