This project involves the basic knowledge of Computer arithmetic in the design of a chip to implement functions like AND, OR, NOT, ADD, SUBTRACT, MULTIPLY and DIVIDE functions. To implement Division, the Goldschmidt Division or division by convergence is used. This is an attractive method because it converges quadratically. To make things easier, a block-by-block approach is followed to get a more clear idea of the Design Flow. The Block level diagram of individual components and the final integration also comes in handy to get clearer view and better understanding of design process. All the basic blocks are described in a higher-level descriptive language and are combined together to make the final module, which performs the desired operation as per the OPCODE given in. The operation of the whole chip is controlled by the Finite State Machine, which is like the “Brain” of the chip. So, careful assignment of states has to be performed. All operations except for the Division take one clock cycle and return to the “General” state after the operation in the next cycle. The Division operation takes eight cycles and hence goes thru eight states then return to “General State” at the end of the eighth cycle. Care should be taken that all the transitions occur only at the positive edge of the clock. All the blocks are tested individually to make sure that all of them are working fine before proceeding to the next block. This way it will be easier at the later stages while debugging the code. Once all the blocks are integrated into the final module an exhaustive test is done to verify the operation of the unit as a whole and any changes if, necessary are made to the code. After this the code is synthesized into the chip using advanced and sophisticated tools like Silicon Ensemble. Once this is done the layout of the chip is again tested for operation and verified using IRSIM, the common switch level simulator.