// ********************************************************************
// POWERALU03
// ********************************************************************
//
// BY:
// ABHINAV GUPTA & IYAD JAFAR
// Version 2.0
// POWERALU03
// ********************************************************************



// ********************************************************************
// BASIC MODULES
// ********************************************************************

// ************************** 2X11 MUX ********************************

module mux2x11(z,in2,in1,select);

input in1;
input in2;
input select;
output z;

assign z = select ? in2 : in1 ;

endmodule

// ************************** Flip-flop with Scan Mode ***************

module dff(z,in,shiftin,scanmode,enable,reset,clock) ;

input shiftin , in , clock , reset , enable , scanmode ;
output z ;
reg z ;
wire out;
wire zero ;

assign zero = 1'b0 ;
mux2x11 mux1(out,shiftin,in,scanmode);

always @ ( posedge clock)
begin
if (reset == 1'b1)
z <= zero;
else
if (enable==1'b1)
z <= out ;
else
z <= z ;
end

endmodule
// ************************** 2X18 MUX ********************************

module mux2x18(z1,inp1,inp2,selecti);

input [7:0] inp1;
input [7:0] inp2;
input selecti;
output [7:0] z1;

assign z1 = selecti ? inp2 : inp1 ;

endmodule

// *************************** 4X18 MUX *******************************

module mux4x18(z,in3,in2,in1,in0,select);

input [7:0] in3;
input [7:0] in2;
input [7:0] in1;
input [7:0] in0;
output [7:0] z ;
input [1:0] select;

assign z = select[1] ? (select[0] ? in3:in2) : (select[0] ? in1:in0);

endmodule


// *************************** General Register ***************************


module reg8(z,in,load,reset,Clk);

input [7:0] in;
input Clk, reset;
input load;
output [7:0] z;
reg [7:0] z;
wire [7:0] zero ;

assign zero = 8'b0000_0000;

always @ (posedge Clk)
begin
if (reset == 1'b1)
z <= zero;
else
if (load == 1'b1)
z <= in;
else
z <= z ;
end


endmodule


// *********************** ScanIn Accumelator ***************************

module scanacc(z,scanout,in,shiftin,scanmode,enable,reset,clock) ;

input shiftin , scanmode, enable , reset , clock ;
input [7:0] in ;
output [7:0] z ;
output scanout ;
wire s;

dff dff0(z[0],in[0],shiftin,scanmode,enable,reset,clock);
dff dff1(z[1],in[1],z[0],scanmode,enable,reset,clock);
dff dff2(z[2],in[2],z[1],scanmode,enable,reset,clock);
dff dff3(z[3],in[3],z[2],scanmode,enable,reset,clock);
dff dff4(z[4],in[4],z[3],scanmode,enable,reset,clock);
dff dff5(z[5],in[5],z[4],scanmode,enable,reset,clock);
dff dff6(z[6],in[6],z[5],scanmode,enable,reset,clock);
dff dff7(z[7],in[7],z[6],scanmode,enable,reset,clock);


assign scanout = z[7] ;

endmodule
// *********************** Addition Modules ***************************

// Half Adder

module ha(sum,carry,a,b);

input a;
input b;
output carry;
output sum;

xor xorsum(sum,a,b);
and andcarry(carry,a,b);

endmodule

// Full Adder

module fa(sum,carry,a,b,cin);

input a;
input b;
input cin;
output carry;
output sum;
wire w1,w2,w3;

xor xorsum(sum,a,b,cin);
and and1(w1,a,b);
and and2(w2,a,cin);
and and3(w3,cin,b);
or or1(carry,w1,w2,w3);

endmodule

// ******************* Modified Addition Modules *********************

// MHA

module mha(sum,carry,a,b,andprev);

input a,b,andprev;
output sum,carry ;
wire w1;

and and1(w1,a,b);
ha ha1(sum,carry,w1,andprev);

endmodule

// MFA

module mfa(sum,carry,a,b,sumprev,cprev);

input a,b,cprev,sumprev;
output sum,carry;
wire w1 ;

and and1(w1,a,b);
fa fa1(sum,carry,w1,sumprev,cprev);

endmodule

// NMFA

module nmfa(sum,carry,a,b,sumprev,cprev);


input a,b,cprev,sumprev;
output sum,carry;
wire w1 ;

nand nand1(w1,a,b);
fa fa1(sum,carry,w1,sumprev,cprev);

endmodule
// *********************** Initial approximation *********************

module initialapp(approx,sign7); // approximation is performed on the
// denomerator only
input sign7;
output [7:0] approx;

assign approx = sign7 ? 8'b1101_0000 : 8'b0011_0000;

endmodule

// ************************* Denumerator Checking ********************

module dcheck(error,denum,muldiv) ; // gives error when the operation is division only

input muldiv ;
input [7:0] denum ;
output error ;
wire w1 ,w2, w3 , w4 , w5 , w6 , w7 ;

nor nor1(w3,denum[7],denum[6],denum[5]) ;
and and1(w1,denum[7],denum[6],denum[5]) ;
or or1 (w2,w3,w1) ; // check the denumerator range

or nor2(w5,denum[7],denum[6],denum[5],denum[4]);
or nor3(w6,denum[3],denum[2],denum[1],denum[0]);
nor (w7,w6,w5) ; // check if denumerator is zero

or or4 (w8,w7,w2) ;

and and2(error,w8,muldiv); //

endmodule

// ************************* Two's Complement *************************

module twoscomp(out2,in) ;

input [7:0] in ;
output [7:0] out2;
wire [7:0] onescomp ;
wire [7:0] cinter ;
wire offset;
wire addone;
assign onescomp[6:0] = ~(in [6:0]);
assign addone = 1'b 1;
assign offset = 1'b0;

fa fa0(out2[0],cinter[0],onescomp[0],offset,addone);
fa fa1(out2[1],cinter[1],onescomp[1],offset,cinter[0]);
fa fa2(out2[2],cinter[2],onescomp[2],offset,cinter[1]);
fa fa3(out2[3],cinter[3],onescomp[3],offset,cinter[2]);
fa fa4(out2[4],cinter[4],onescomp[4],offset,cinter[3]);
fa fa5(out2[5],cinter[5],onescomp[5],offset,cinter[4]);
fa fa6(out2[6],cinter[6],onescomp[6],offset,cinter[5]);
// fa fa7(out2[7],cinter[7],onescomp[7],offset,cinter[6]);
assign out2[7] = in[7];
endmodule



// ************************ RNE module ******************************
module rne(out2,in) ;

input [9:0] in;
output [7:0] out2;
wire w1,w2,offset ,ulp;
wire [7:0] cinter;

and and1(w1,in[0],in[1]); // ULP logic
and and2(w2,in[1],in[2]); // ULP = (in0 & in1) + (in1 & in2)
or or1(ulp,w1,w2);

assign offset = 1'b0;

fa fa0(out2[0],cinter[0],in[2],offset,ulp);
fa fa1(out2[1],cinter[1],in[3],offset,cinter[0]);
fa fa2(out2[2],cinter[2],in[4],offset,cinter[1]);
fa fa3(out2[3],cinter[3],in[5],offset,cinter[2]);
fa fa4(out2[4],cinter[4],in[6],offset,cinter[3]);
fa fa5(out2[5],cinter[5],in[7],offset,cinter[4]);
fa fa6(out2[6],cinter[6],in[8],offset,cinter[5]);
fa fa7(out2[7],cinter[7],in[9],offset,cinter[6]);

endmodule

// ******************** Adder - Subtractor 1-bit ********************

module addsub1(sum,carry,a,b,binv,cin);

input a;
input b;
input binv,cin;
output carry;
output sum;
wire w1,w2,w3,w4;

xor xorinvert(w4,b,binv); //compliments B
xor xorsum(sum,a,w4,cin);
and and1(w1,a,w4);
and and2(w2,a,cin);
and and3(w3,cin,w4);
or or1(carry,w1,w2,w3);

endmodule


// *****************************************************************
// Mltiplier's Basic Modules
// *****************************************************************

// ************************ Stage One ******************************

module stageone(out,in,b);

input [7:0] in;
input b ;
output [7:0] out ;

and and0(out[0],in[0],b);
and and1(out[1],in[1],b);
and and2(out[2],in[2],b);
and and3(out[3],in[3],b);
and and4(out[4],in[4],b);
and and5(out[5],in[5],b);
and and6(out[6],in[6],b);
nand nand0(out[7],in[7],b);

endmodule

// ************************ Stage Two ******************************

module stagetwo(sumha,cha,out_stage1,a8,b);

input b;
input [7:0] out_stage1;
input [7:0] a8;
output [7:0] sumha;
output [6:0] cha;

mha mha0(sumha[0],cha[0],a8[0],b,out_stage1[1]);
mha mha1(sumha[1],cha[1],a8[1],b,out_stage1[2]);
mha mha2(sumha[2],cha[2],a8[2],b,out_stage1[3]);
mha mha3(sumha[3],cha[3],a8[3],b,out_stage1[4]);
mha mha4(sumha[4],cha[4],a8[4],b,out_stage1[5]);
mha mha5(sumha[5],cha[5],a8[5],b,out_stage1[6]);
mha mha6(sumha[6],cha[6],a8[6],b,out_stage1[7]);
nand nand7(sumha[7],a8[7],b);

endmodule

// *********************** Stage Three *****************************

module stagethree(sumfa,cfa,a8,b,out_stage2_sum,out_stage2_carry);

input b;
input [7:0] out_stage2_sum;
input [6:0] out_stage2_carry;
input [7:0] a8;
output [7:0] sumfa;
output [6:0] cfa;

mfa mfa0(sumfa[0],cfa[0],a8[0],b,out_stage2_sum[1],out_stage2_carry[0]);
mfa mfa1(sumfa[1],cfa[1],a8[1],b,out_stage2_sum[2],out_stage2_carry[1]);
mfa mfa2(sumfa[2],cfa[2],a8[2],b,out_stage2_sum[3],out_stage2_carry[2]);
mfa mfa3(sumfa[3],cfa[3],a8[3],b,out_stage2_sum[4],out_stage2_carry[3]);
mfa mfa4(sumfa[4],cfa[4],a8[4],b,out_stage2_sum[5],out_stage2_carry[4]);
mfa mfa5(sumfa[5],cfa[5],a8[5],b,out_stage2_sum[6],out_stage2_carry[5]);
mfa mfa6(sumfa[6],cfa[6],a8[6],b,out_stage2_sum[7],out_stage2_carry[6]);
nand nand7(sumfa[7],a8[7],b);

endmodule

// ************************* Stage Four *****************************

module stagefour(sumnfa,cnfa,a8,b,out_stage3_sum,out_stage3_carry);

input b;
input [7:0] out_stage3_sum;
input [6:0] out_stage3_carry;
input [7:0] a8;
output [7:0] sumnfa;
output [6:0] cnfa;

nmfa nmfa0(sumnfa[0],cnfa[0],a8[0],b,out_stage3_sum[1],out_stage3_carry[0]);
nmfa nmfa1(sumnfa[1],cnfa[1],a8[1],b,out_stage3_sum[2],out_stage3_carry[1]);
nmfa nmfa2(sumnfa[2],cnfa[2],a8[2],b,out_stage3_sum[3],out_stage3_carry[2]);
nmfa nmfa3(sumnfa[3],cnfa[3],a8[3],b,out_stage3_sum[4],out_stage3_carry[3]);
nmfa nmfa4(sumnfa[4],cnfa[4],a8[4],b,out_stage3_sum[5],out_stage3_carry[4]);
nmfa nmfa5(sumnfa[5],cnfa[5],a8[5],b,out_stage3_sum[6],out_stage3_carry[5]);
nmfa nmfa6(sumnfa[6],cnfa[6],a8[6],b,out_stage3_sum[7],out_stage3_carry[6]);
and and7(sumnfa[7],a8[7],b);

endmodule

//*************************** Stage five *****************************

module stagefive(sum5fa,out_stage4_sum,out_stage4_carry);

input [7:0] out_stage4_sum;
input [6:0] out_stage4_carry;
output [7:0] sum5fa;
wire [6:0] w1;
wire one;

assign one =1'b1;
fa fa0(sum5fa[0],w1[0],out_stage4_sum[1],out_stage4_carry[0],one);
fa fa1(sum5fa[1],w1[1],out_stage4_sum[2],out_stage4_carry[1],w1[0]);
fa fa2(sum5fa[2],w1[2],out_stage4_sum[3],out_stage4_carry[2],w1[1]);
fa fa3(sum5fa[3],w1[3],out_stage4_sum[4],out_stage4_carry[3],w1[2]);
fa fa4(sum5fa[4],w1[4],out_stage4_sum[5],out_stage4_carry[4],w1[3]);
fa fa5(sum5fa[5],w1[5],out_stage4_sum[6],out_stage4_carry[5],w1[4]);
fa fa6(sum5fa[6],w1[6],out_stage4_sum[7],out_stage4_carry[6],w1[5]);
not n1(sum5fa[7],w1[6]);

endmodule

// ********************************************************************
// Multiplier Integration
// ********************************************************************


module multiplier(result8,a,b,muldiv);

input [7:0] a;
input [7:0] b;
input muldiv ;

/* signal to choose the extracted bits depending on the operation.
if muldiv = 0 then multiply. */

output [7:0] result8;

wire [9:0] mult16;
wire [9:0] div16;
wire [9:0] selected_operation;
wire [7:0] w1;
wire [7:0] w2;
wire [6:0] w3;
wire [7:0] w4;
wire [6:0] w5;
wire [7:0] w6;
wire [6:0] w7;
wire [7:0] w8;
wire [6:0] w9;
wire [7:0] w10;
wire [6:0] w11;
wire [7:0] w12;
wire [6:0] w13;
wire [7:0] w14;
wire [6:0] w15;
wire [7:0] w16; // stores the 16 bit result of the multiplier
wire [15:0] total16;


stageone row0(w1,a,b[0]);

stagetwo row1(w2,w3,w1,a,b[1]);

stagethree row2(w4,w5,a,b[2],w2,w3);

stagethree row3(w6,w7,a,b[3],w4,w5);

stagethree row4(w8,w9,a,b[4],w6,w7); //p4 = w8[0]

stagethree row5(w10,w11,a,b[5],w8,w9); //p5 = w10[0]

stagethree row6(w12,w13,a,b[6],w10,w11); //p6= w12[0]

stagefour row7(w14,w15,a,b[7],w12,w13); //p7 = w14[0]

stagefive row8(w16,w14,w15);


// The total 16 bit result

assign total16[0] = w1[0];
assign total16[1] = w2[0];
assign total16[2] = w4[0];
assign total16[3] = w6[0];
assign total16[4] = w8[0];
assign total16[5] = w10[0];
assign total16[6] = w12[0];
assign total16[7] = w14[0];
assign total16[15:8] = w16[7:0];

// Bits extraction for multiplication result

assign mult16[8:0] = total16[13:5];
assign mult16[9] = total16[15];

// Bits extraction for division result

assign div16[8:0] = total16[12:4];
assign div16[9] = total16[15];

// select the result

assign selected_operation [9:0] = muldiv ? div16[9:0] : mult16[9:0] ;

// passing the result to RNE

rne rne1(result8,selected_operation) ;

endmodule


// ********************************************************************
// Adder/Subtractor Module
// ********************************************************************

module addsub8(result,cout,of,acc,b,binv);

input [7:0] acc;
input [7:0] b;
input binv;
output cout,of;
output [7:0] result;
wire [6:0] w;

addsub1 bit0(result[0],w[0],acc[0],b[0],binv,binv);
addsub1 bit1(result[1],w[1],acc[1],b[1],binv,w[0]);
addsub1 bit2(result[2],w[2],acc[2],b[2],binv,w[1]);
addsub1 bit3(result[3],w[3],acc[3],b[3],binv,w[2]);
addsub1 bit4(result[4],w[4],acc[4],b[4],binv,w[3]);
addsub1 bit5(result[5],w[5],acc[5],b[5],binv,w[4]);
addsub1 bit6(result[6],w[6],acc[6],b[6],binv,w[5]);
addsub1 bit7(result[7],cout,acc[7],b[7],binv,w[6]);

xor xorof(of,w[6],cout); // check for overflow in add/sub

endmodule


// ********************************************************************
// AOI Module
// ********************************************************************

module aoi(aoi_out,acc,b,select_aoi);

input [7:0] acc;
input [7:0] b ;
input [1:0] select_aoi;
output [7:0] aoi_out ;
wire [7:0] andout;
wire [7:0] orout;
wire [7:0] notout;
wire [7:0] floating;

assign floating = 8'bxxxx_xxxx;

assign andout = acc & b;
assign orout = acc | b;
assign notout = ~(acc) ;

mux4x18 muxout(aoi_out,floating,notout,orout,andout,select_aoi);

endmodule

// ********************************************************************
// Squareroot
// ********************************************************************

module sqrt(out,in);

input [7:0] in ;
output [7:0] out ;
wire [7:0] constant ;
wire [7:0] shift;
wire binv , cout , of;

assign binv = 1'b1 ;
assign constant = 8'b0110_0000 ;
assign shift [6:0] = in [7:1] ;
assign shift [7] = 1'b0 ;

addsub8 subunit(out,cout,of,constant,shift,binv);

endmodule
// ********************************************************************
// Divider Module
// ********************************************************************

module divder(result,acc,denum,select_muxa,select_muxb,loada,loadb,loadc,muldiv,reset,clock);

input [7:0] acc;
input [7:0] denum;
input [1:0] select_muxa;
input [1:0] select_muxb;
input loada,loadb,loadc,clock,reset,muldiv;
output [7:0] result;

wire [7:0] approx;
wire [7:0] muxa_out;
wire [7:0] muxb_out;
wire [7:0] mult_out;
wire [7:0] twos_out;
wire [7:0] rega_out;
wire [7:0] regb_out;
wire [7:0] regc_out;
wire [7:0] notused;

assign notused = 8'b1010_1010;

initialapp app(approx,denum[7]);
mux4x18 muxa(muxa_out,notused,approx,denum,rega_out,select_muxa);
mux4x18 muxb(muxb_out,regc_out,regb_out,acc,denum,select_muxb);
multiplier m1(mult_out,muxa_out,muxb_out,muldiv);
twoscomp twos(twos_out,mult_out);
reg8 rega(rega_out,twos_out,loada,reset,clock);
reg8 regb(regb_out,mult_out,loadb,reset,clock);
reg8 regc(regc_out,mult_out,loadc,reset,clock);


assign result = mult_out;

endmodule


// ********************************************************************
// Finite State Machine
// ********************************************************************

module controller(select_result,aoi_select,binvert,enable_acc,select_muxa,select_muxb,
loada,loadb,loadc,muldiv,busy,idle,opcode,reset,scanmode,clock);

input clock, reset,scanmode ;
input [3:0] opcode;
output [1:0] select_muxa;
output [1:0] select_muxb;
output [1:0] aoi_select;
output [1:0] select_result;
output binvert, muldiv, loada, loadb, loadc , enable_acc , busy , idle ;



reg binvert, muldiv, loada, loadb, loadc , enable_acc , busy , idle ;
reg [1:0] aoi_select;
reg [1:0] select_muxa;
reg [1:0] select_muxb;
reg [1:0] select_result;

parameter [2:0]


general = 3'b000,
gdiv1 = 3'b001,
gdiv2 = 3'b010,
gdiv3 = 3'b011,
gdiv4 = 3'b100,
gdiv5 = 3'b101,
gdiv6 = 3'b110,
gdiv7 = 3'b111;

/*S0 =
S1 = 3'b0001,
S2 = 3'b0010,
S3 = 3'b0011,
S4 = 3'b0100,
S5 = 3'b0101,
S6 = 3'b0110,
S7 = 3'b0111;*/

reg [2:0] CURRENT_STATE; // to save the value
reg [2:0] NEXT_STATE;



always @(posedge clock)

begin
if (reset == 1'b1)
CURRENT_STATE<= general;
else
CURRENT_STATE <= NEXT_STATE; //output the new state

end


always @(CURRENT_STATE or opcode or scanmode )

begin
case(CURRENT_STATE)

general:

if (scanmode == 1'b1 ) // Enable the accumelator for the scan mode
begin
enable_acc <=1'b1;
busy <= 1'b1 ;
idle <=1'b0;
aoi_select <= 2'b00;
binvert <= 1'b0;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b00;
NEXT_STATE <= general;
end

//--------------------------
else if (opcode == 4'b0000) // No operation
begin
enable_acc <= 1'b0;
busy <= 1'b0 ;
idle <=1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b00;
NEXT_STATE <= general;
end

//--------------------------

else if(opcode == 4'b0001) // Addition
begin
binvert <= 1'b0;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
aoi_select <= 2'b00;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b00 ;
NEXT_STATE <= general;
end

//--------------------------

else if (opcode == 4'b0010) // Subtraction
begin
binvert <= 1'b1;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
aoi_select <= 2'b00;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b00 ;
NEXT_STATE <= general;
end

//--------------------------
else if (opcode == 4'b0011) // And
begin
aoi_select <= 2'b00 ;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
binvert <= 1'b0;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b01 ;
NEXT_STATE <= general;
end
//--------------------------

else if (opcode == 4'b0100) // OR
begin
aoi_select<= 2'b01 ;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
binvert <= 1'b0;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
select_result <= 2'b01 ;
NEXT_STATE <= general;
end

//--------------------------
else if (opcode == 4'b0101) // Load
begin
select_result <= 2'b11 ;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
binvert <= 1'b0;
aoi_select<= 2'b00 ;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
muldiv <= 1'b0;
NEXT_STATE <= general;
end
//--------------------------

else if (opcode == 4'b0110) //Division
begin
enable_acc <= 1'b0;
busy <= 1'b1 ;
idle <=1'b0;
muldiv <=1'b1 ;
select_muxa <= 2'b10;
select_muxb <= 2'b01;
binvert <= 1'b0;
aoi_select<= 2'b00 ;
loada <= 1'b0;
loadc <= 1'b0;
loadb <=1'b1;
select_result <= 2'b00 ;
NEXT_STATE <= gdiv1;
end

//--------------------------

else if (opcode == 4'b0111) //multiplication
begin
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
muldiv <=1'b0 ;
select_muxa <= 2'b01;
select_muxb <= 2'b01;
select_result <= 2'b10;
aoi_select<= 2'b00 ;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b0;
binvert <= 1'b0;

NEXT_STATE <= general ;
end

//--------------------------

else // Not
begin
aoi_select<= 2'b10 ;
enable_acc <= 1'b1;
busy <= 1'b1 ;
idle <=1'b0;
select_result <= 2'b01 ;
muldiv <=1'b0 ;
select_muxa <= 2'b00;
select_muxb <= 2'b00;
loada <= 1'b0;
loadc <= 1'b0;
loadb <=1'b0;
binvert <= 1'b0;
NEXT_STATE <= general;
end


gdiv1:

begin
muldiv <= 1'b1;
idle <=1'b0;
select_muxa <= 2'b10 ;
select_muxb <= 2'b00 ;
loada <= 1'b1;
loadc <= 1'b1;
loadb <= 1'b0;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
busy <= 1'b1;

NEXT_STATE <= gdiv2;

end

gdiv2:

begin
select_muxa <= 2'b00;
select_muxb <= 2'b10;
idle <=1'b0;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
busy <= 1'b1;
muldiv <=1'b1;

NEXT_STATE <= gdiv3;

end

gdiv3:

begin
select_muxa <= 2'b00;
loadb <= 1'b0;
idle <=1'b0;
select_muxb <= 2'b11;
loada <= 1'b1;
loadc <= 1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
muldiv <=1'b1;

busy <= 1'b1;
NEXT_STATE <= gdiv4;

end

gdiv4:

begin
select_muxa <= 2'b00;
select_muxb <= 2'b10;
idle <=1'b0;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
muldiv <=1'b1;
busy <= 1'b1;

NEXT_STATE <= gdiv5;

end

gdiv5:

begin
select_muxa <= 2'b00;
loadb <= 1'b0;
idle <=1'b0;
select_muxb <= 2'b11;
loada <= 1'b1;
loadc <= 1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
muldiv <=1'b1;
busy <= 1'b1;

NEXT_STATE <= gdiv6;
end

gdiv6:

begin
select_muxa <= 2'b00;
select_muxb <= 2'b10;
idle <=1'b0;
loada <= 1'b0;
loadc <= 1'b0;
loadb <= 1'b1;
aoi_select <= 2'b00;
binvert <= 1'b0;
enable_acc <= 1'b0;
select_result <= 2'b00 ;
muldiv <=1'b1;
busy <= 1'b1;

NEXT_STATE <= gdiv7;

end

gdiv7:

begin
loadb <= 1'b0;
enable_acc <= 1'b1;
idle <=1'b0;
select_result <= 2'b10;
select_muxa <= 2'b00;
select_muxb <= 2'b10;
loada <= 1'b0;
loadc <= 1'b0;
aoi_select <= 2'b00;
binvert <= 1'b0;
busy <= 1'b1;
muldiv <=1'b1;

NEXT_STATE <= general;
end

endcase // case(CURRENT_STATE)

end // always@ (CURRENT_STATE or opcode)

endmodule // controller



// ********************************************************************
// Power ALU03
// ********************************************************************

module topcell(acc_out,scanout,error,busy,idle,of,data_in,opcode,reset,scanmode,scanin,clock) ;

input reset , clock , scanmode , scanin ;
input [3:0] opcode ;
input [7:0] data_in ;
output of , busy , idle , scanout , error ;
output [7:0] acc_out ;

wire loada , lodab , loadc , muldiv , binvert , enable_acc , cout;
wire [1:0] select_muxa;
wire [1:0] select_muxb;
wire [1:0] aoi_select;
wire [1:0] select_result;

wire [7:0] acc_data;
wire [7:0] divmult2;
wire [7:0] aoi1;
wire [7:0] addsub0;
wire [7:0] acc_data_in;


controller brain(select_result,aoi_select,binvert,enable_acc,select_muxa,select_muxb,loada,loadb,loadc,
muldiv,busy,idle,opcode,reset,scanmode,clock);

divder divmult1(divmult2,acc_out,data_in,select_muxa,select_muxb,loada,loadb,loadc,muldiv,reset,clock);

aoi aoiout(aoi1,acc_out,data_in,aoi_select);

addsub8 addsub1(addsub0,cout,of,acc_out,data_in,binvert);

mux4x18 outputmux(acc_data_in,data_in,divmult2,aoi1,addsub0,select_result);

scanacc acc(acc_out,scanout,acc_data_in,scanin,scanmode,enable_acc,reset,clock) ;

dcheck dcheck1(error,data_in,muldiv) ;


endmodule


// ********************************************************************
// End of Code // ********************************************************************
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