3.8 FINITE STATE MACHINE
The finite state machine is in fact the brain for the chip since it will accept some inputs and upon those issues the signals required to control the operation of the chip. In few words, the FSM is a certain number of flip-flops connected in a specific scheme along with some logic gates so that they transfer from one logical state to another upon the application of some input signals and changes the values of some outputs.
For POWERALU03, the finite state machine inputs and output control signals and their description are listed in table 2. To implement the FSM in Verilog, two concurrent ALWAYS constructs are required. The first one assigns the next stat of the flip-flops to the current state and the second one calculates the next state in the form of if-else structure depending on the value of the opcode. In this chip all operation were done in the first state – general state- except the division which required additional seven states to perform four iteration steps - div1 through div7-.
|
Direction |
Signal Name |
Size |
Description |
|
INPUT |
Opcode |
4 |
Determine the operation to be carried out |
|
Reset |
1 |
Master reset for the whole chip. All registers are reset |
|
|
Clock |
1 |
Master clock for the chip |
|
|
Scanmode |
1 |
Put the chip in scanmode |
|
|
OUTPUT |
Select_aoi |
2 |
Select the logical operation from AOI unit |
|
Binv |
1 |
Put the add/sub unit in addition or subtraction mode |
|
|
Busy |
1 |
Chip is executing previous opcode |
|
|
Idle |
1 |
Chip is ready to receive new data and opcode |
|
|
Enable_acc |
1 |
Enable the accumulator to store the new result |
|
|
Select_result |
2 |
Select the result calculated from specific unit |
|
|
Muldiv |
1 |
Put the division unit in multiplication or division state and in which mode the RNE operates |
|
|
Loada |
1 |
Load register A in division unit |
|
|
Loadb |
1 |
Load register B in division unit |
|
|
loadc |
1 |
Load register C in division unit |
|
|
Select_muxa |
2 |
Select multiplexer A in division unit |
|
|
Select_muxb |
2 |
Select multiplexer B in division unit |
Table 2: FSM input/output control signals
To follow how these output signals are changed in the FSM, table 3 lists the different opcodes used and the corresponding values for the control signals. To make the implementation of the FSM more stable and convenient, any unesed signal in a certain state was assigned to be logic zero instead of making it don’t care.
|
opcode |
Next state |
Select_aoi |
Binv |
Select_muxa |
Select_muxb |
Loada |
Loadb |
Loadc |
Muldiv |
Select_result |
Enable_acc |
Busy |
Idle |
|
0000 |
GEN |
00 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
00 |
1 |
0 |
0 |
|
0001 |
GEN |
00 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
00 |
1 |
1 |
0 |
|
0010 |
GEN |
00 |
1 |
00 |
00 |
0 |
0 |
0 |
0 |
00 |
1 |
1 |
0 |
|
0011 |
GEN |
00 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
01 |
1 |
1 |
0 |
|
0100 |
GEN |
01 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
01 |
1 |
1 |
0 |
|
0101 |
GEN |
10 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
11 |
1 |
1 |
0 |
|
0110 |
DIV1 |
00 |
0 |
01 |
01 |
0 |
1 |
0 |
0 |
10 |
0 |
1 |
0 |
|
0111 |
GEN |
00 |
0 |
01 |
10 |
0 |
0 |
0 |
1 |
01 |
1 |
1 |
0 |
|
1000 |
GEN |
10 |
0 |
00 |
00 |
0 |
0 |
0 |
0 |
01 |
1 |
1 |
0 |
Table 3: FSM signals assignment
For the division operation , the chip will go through consequtive seven states in which the control signals for the division blocks are chagning continuously evry clock cycle. Seven states were required to complete because the first one was excuted in the general state. Table 4 shows how the values for the control signals in the division block are changed.
|
Cycle |
Cureent state |
Next state |
muxA |
muxB |
loada |
loadb |
loadc |
muldiv |
|
1 |
General |
Div1 |
10 |
01 |
0 |
1 |
0 |
1 |
|
2 |
Div1 |
Div2 |
10 |
00 |
1 |
0 |
1 |
1 |
|
3 |
Div2 |
Div3 |
00 |
10 |
0 |
1 |
0 |
1 |
|
4 |
Div3 |
Div4 |
00 |
11 |
1 |
0 |
1 |
1 |
|
5 |
Div4 |
Div5 |
00 |
10 |
0 |
1 |
0 |
1 |
|
6 |
Div5 |
Div6 |
00 |
11 |
1 |
0 |
1 |
1 |
|
7 |
Div6 |
Div7 |
00 |
10 |
0 |
1 |
0 |
1 |
|
8 |
Div7 |
General |
00 |
11 |
1 |
0 |
1 |
1 |
Table 4: state transition for the division operation