3.7 DIVISION ITERATION AND MULTIPLICATION

This unit is supposed to perform division on two 8-bit fractional operands in the range [-1,-2) and [1, 2) which means that the number format is 2.6. The Goldschmidt Division method for division would be best implemented by considering calculation of the quotient Q = N/D using four steps:

1. Obtain an initial reciprocal approximation, K1=1/D.

2. Perform an iterative improvement of the denominator (k times), where R_i=R_i-1. K_i, such that R₀ = D.

3. Perform an iterative improvement of the new numerator (k times), Q_i= Q_i-1.K_i, such that Q₀ = N

4. Get ready for the next iteration, by normalizing the denominator by performing K_i+1= (2-R_i).

   To implement this in hardware, it is obvious that the division operation is simply a multiplication process of some values. So the CSAM multiplier was incorporated into the division unit along with three pipeline registers to store the intermediate values of consecutive iterations. Two 8-bit 4:1 multiplexers were used to make the selection for the values to be multiplied. The selection signals for the multiplexers are issued by the FSM. To fully complete the division unit, three other modules were needed. The first one is the module that produces the initial approximation constant (K0). The second one is the one which calculates K_i+1 = 2-R_i. The final module is the rounding module which extracts the 8-bit result out of the 16-bit given from the CSAM.

3.7.1 INITIAL APPROXIMATION UNIT

 As mentioned before, this module gives the initial value for the first iteration in the division. Since division is for numbers between [1, 2) and [-1,-2) it was suitable to pick the initial approximation to be 0.75 or -0.75 depending on the sign of the denominator. So the most significant bit of the denominator was used as a selection signal for an 8-bit 2:1 multiplexer whose inputs are 0.75 and -0.75.  

3.7.2 TWOS COMPLEMENT UNIT

This unit calculates the new value for the iterative constant K by performing the operation K_i+1 = 2-R_i. In hardware this operation was found to be equivalent to finding the twos complement of the first seven bits and keeping the most significant – the sign - bit unchanged.

3.7.3 ROUNDING UNIT

Since the multiplier’s result is 16-bit and the registers in the chip are only 8-bit long, it was necessary to find an appropriate way to round the answer other than truncation. The method used was IEEE 754 standard which is called round to nearest even (RNE). In this standard the value of ULP is calculated depending on three bits of the number to be rounded. The first bit is the last bit (L) before the truncation point and the other two bits (G, R) are those after the truncation point as seen in figure 7. To generate the ULP, table 1 shows truth table for this value which is simply added to the number.