5. RESULTS
The designed chip was thoroughly tested at all sub stages and the final stage to make sure that all operation inside the chip are running perfectly. Special test benches were written in Verilog for each sub unit and for the final unit. The results for the final chip testbench are attached in the appendix. After that the chip was synthesized using Synopsys and silicon ensemble to produce the layout for the chip with both pads and not padded. The layout was then tested by IRSIM to check the functionality. The layouts and the timing simulation results are attached in the appendix.
The main constraints for the chip design were the area and the speed. For the POWERALU03 the designed chip was found o be able to run at 75 MHz approximately. For the area constraint, the core area was found to 0.8 mm2 without the pads and 2.25 mm2.
Two main troubles were faced during the design. The first one was how to make the chip distinguish between the two different number formats in division and multiplication. The second one was the problem of latch inference during synthesis.
SIGNAL SCAN RESULTS
IRSIM RESULTS
MAGIC LAYOUT
6. CONCLUSIONS
Being involved in such designs for digital systems is full of experience and knowledge starting from basic Boolean algebra and ending with synthesis and fabrication of integrated circuits. Nevertheless careful testing and enough patience is required to obtain a working and bug free digital system.